Equalizing driver circuits are often used in high-speed signaling systems to mitigate the effects of inter-symbol interference (ISI) and inductive coupling between neighboring signal paths (i.e., crosstalk). FIG. 1 illustrates ISI in a prior-art signaling system in which data is transmitted as a series of distinct signal levels. At time T1, a logic 0 signal is transmitted on a signal line by pulling the line up to level VH. Subsequently, at time T2, a logic 1 is transmitted by pulling the line down to level VL. Finally, at time T3, a logic 0 is transmitted again by pulling the signal line up to VH. Because of the signal driving circuit has finite drive strength (i.e., finite ability to sink and source current), the voltage level of the signal line does not change instantaneously at time T2 or time T3, but rather exhibits a finite slew rate. Consequently, the ideal times for sampling (i.e., in a receiving circuit) the signals output at times T1, T2 and T3 occur at sample times S1, S3 and S3, respectively; after the signal has transitioned to a relative minimum or maximum level and before the signal begins transitioning to a next level. Referring to sample time S2 in particular, note that the level of the signal is affected not only by the logic 1 output at time T2, but also by the logic 0 output at time T1 which, due to the finite slew rate of the transmitter, limits the ability of the signal level to reach and settle at VL. The signal at sample time S2 is also affected by the logic 0 transmitted at time T3 which limits the ability of the signal level to settle and hold at VL. Thus, values transmitted before and after the signal transmitted at time T2 interfere with the level of the T2 signal at the receiver due to ISI.
FIG. 2 illustrates a prior-art output driver 100 in which ISI is reduced by dynamically increasing and decreasing the signal drive strength of the output driver 100 according to the relationship between past, present and future transmit data (TDATA). For example, if a logic 1 is to be transmitted (present data=1), but a logic zero was transmitted previously, the drive strength of the output driver 100 is temporarily increased to achieve faster slew from the logic 0 to logic 1 signal levels, thereby reducing the ISI caused by the previous transmission. Similarly, if a logic 1 is to be transmitted followed by a logic 0, the drive strength of the output driver is temporarily increased to reduce the ISI caused by the subsequent transmission. Such dynamic adjustments to the drive strength of the output driver 100 are referred to as equalization operations, and the output driver is said to be an equalizing output driver.
The output driver 100 includes three sub-driver circuits formed by respective current-sinking drive transistors (109, 111, 113) and corresponding bias current sources (110, 112, 114). The sub-driver circuits drive future, present and past data values, /A, B and /C, respectively (the ‘/’ symbol indicating complement), onto a signal path 102 that is pulled up to a supply voltage through resistor, R. Flip-flops 105 and 107 are coupled in series to form a shift register for producing the present and past data values, B and /C, by shifting an incoming data signal, TDATA (i.e., /A), in response to a transmit clock signal, TCLK. Thus, during a given cycle of the transmit clock signal, /A represents a data value to be transmitted in a subsequent cycle, B represents a data value to be transmitted in the present clock cycle, and /C represents a data value transmitted during the previous clock cycle. The bias currents produced by current sources 110, 112 and 114 are 0.1l, 0.8l and 0.1l, respectively, so that the present data value, when high, draws current 0.8l (i.e., by switching on transistor 111) to pull the output line 102 low, and the future and past values, when low, each draw current 0.1l (i.e., by switching on transistors 109 and 113, respectively) to pull the output line low 102 by incremental amounts.
FIG. 3 illustrates the effect of the future, present and past data values on the total current drawn by the prior-art output driver 100 of FIG. 2. At time T1, the future, present and past data values (i.e., AT1, BT1 and CT1) are all zero so that, referring to FIG. 2, transistors 109 and 113 are switched on (i.e., due to the inversions of values A and C), and transistor 111 is switched off. Accordingly, the output driver sinks a current of 0.2l to represent a steady-state logic 0 condition and the voltage level of output line is pulled down slightly to a nominal, VH level. At time T2, the values of A, B, and C are shifted such that CT2=BT1=0, BT2=AT1=0, and AT2=1. In this state, the current drawn by the output driver is reduced from 0.2l to 0.1l to counteract the ISI that would otherwise result from subsequent transmission of a logic 1 value (i.e., at time T3).
At time T3, the values of A, B, and C are shifted again such that BT3=AT2=1, CT3=BT2=0, and AT3=1. Because B is high and C is low, the output driver sinks a current of 0.9l; 0.8 l via transistor 111 and 0.1l via transistor 113. This current level may be understood by viewing the 0.8l drawn by transistor 111 as being a nominal current needed to produce the present logic 1 value, plus a current 0.1l drawn by transistor 113 to counteract the ISI from the logic 0 transmitted during the preceding transmission interval.
At time, T4, the present, past and future values are all high (i.e., AT4=BT4=CT4=1), so that a current of 0.8l is drawn to represent the steady-state logic 1 condition. Finally, at time T5, the present and past values remain at logic 1 (i.e., B=C=1), but the future value, A, becomes a logic 0. Consequently, the current drawn by the output driver increases from 0.8l to 0.9l to counteract the ISI from the subsequent logic 0 transmission.
Referring again to FIG. 2, signal equalization is achieved by the output driver 100 by driving the output signal line with two additional sub-driver circuits (i.e., sub-driver circuits for past and future data). Because each sub-driver exhibits a parasitic capacitance, Ci, the net affect of coupling additional sub-driver circuits to the output signal line is to increase the total parasitic capacitance of the output driver 100 from Ci to 3Ci. This presents a significant problem in high-speed signaling systems, where the parasitic capacitance of the output driver tends to be a dominant, bandwidth-limiting capacitance of the signaling system. Additionally, transmission paths in high-speed signaling systems are often terminated by termination elements having impedances selected to match the impedance of the transmission paths (i.e., as shown in FIG. 2, R is chosen to match Z0), thereby reducing undesired signal reflections. The increased parasitic capacitance of the equalizing output driver produces a mismatch between the effective termination impedance and the transmission path impedance, thereby increasing the level of signal reflections on the transmission path. Thus, it would be desirable to provide an equalizing output driver having reduced parasitic capacitance.